WD preparing to ship flash chips with half a terabit of capacity

The new chips increase capacity by 40%

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Western Digital (WD) has begun manufacturing the third generation of its 3D NAND flash chips, which increases the number of layers from 48 to 64 and will allow it to double capacity.

Pilot production of the new 64-layer chips has already started in WD's Yokkaichi, Japan joint venture fabrication plant; initial shipments are expected in the fourth quarter of this year with "meaningful commercial volumes" beginning in the first half of 2017.

screen shot 2015 08 04 at 5.10.00 pm Toshiba

Toshiba's 48-layer 3D NAND chips.

In 2015, SanDisk and its technology partner Toshiba announced it was manufacturing the world's first 48-layer 3D NAND product using BiCS (Bit-Cost Scalable NAND) technology. That BiCS NAND flash chip offered 256Gbit (32GB) of capacity and stored 3-bit-per-cell (transistor). The latest iteration of the technology is called BiCS3.

According to Toshiba, the new 64-layer chips have 40% more potential capacity over the previous BiCS2 technology.

BiCS 3D NAND Toshiba Toshiba

SanDisk and Toshiba announced last year they are manufacturing 256Gbit (32GB), 3-bit-per-cell (X3) 48-layer 3D NAND flash chips that offer twice the capacity of the next densest memory. The 3D NAND technology is called BiCS, short for Bit Cost Scaling.

In March, SanDisk shareholders approved a $19 billion buyout by Western Digital.

BiCS3, which is still jointly being developed with manufacturing partner Toshiba, will be initially deployed in 256Gbit capacities. But it will be available in a range of capacities up to half a terabit on a single chip.

Unlike 2D or planar NAND, which consists of a flat layer of NAND flash cells, 3D NAND stacks the cells vertically like a skyscraper.

sandisk 3d nand slide SanDisk

As 2D NAND approaches scaling limits due to lithography size and error rates, layer stacking to produce 3D NAND obviates those concerns. This image shows horizontally stacked conductive polysilicon layers around a central memory hole that provide the stacked NAND bits. The circular hole minimizes neighboring bit disturb and allows overall density to rise.

"The launch of the next generation 3D NAND technology based on our industry-leading 64-layer architecture reinforces our leadership in NAND flash technology," Siva Sivaram, executive vice president of WD memory technology, said in a statement. "BiCS3 will feature the use of 3-bits-per-cell technology along with advances in high aspect ratio semiconductor processing to deliver higher capacity, superior performance and reliability at an attractive cost."

WD is not alone in its development of 3D NAND. In 2013, Samsung became the first to introduce a vertical TLC "V-NAND," a 32-layer cell structure based on Charge Trap Flash (CTF) and vertical interconnect process technology to link the cell array.

In 2014, Samsung began shipping its 32-layer "V-NAND" (vertical NAND) SSDs and last year released a 48-layer product. The company even announced it was working on  a 15TB prototype desktop SSD.

Intel and its SSD partner Micron have also announced 48-layer 3D NAND. The two companies are preparing to launch a resistive RAM (ReRAM) product called 3D Xpoint (which will be sold under the name "Optane") later this year. That non-volatile memory will be up to 1,000 times faster than NAND flash and have 1,000 times the endurance -- but it's expected to be more expensive. Initially, 3D XPoint memory will store 128Gbits per die across two stacked memory layers.

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3D XPoint technology is a new class of memory from Intel and Micron that relies on resistance change of the bulk material to achieve non-volatility.  3D XPoint technology uses the bulk material to switch resistance state and does not rely on statistically variable filaments. The combination of architecture and unique materials in both the memory cell and selector enable 3D XPoint to achieve higher density and better performance and endurance.

From the first iteration, 3D NAND flash technology offered from two to 10 times higher reliability and twice the write performance of planar NAND.

Most importantly, however, 3D NAND removed the lithography barrier planar (single-level NAND flash) faced as manufacturers shrunk transistors below 15 nanometers in size. The smaller lithography process led to data errors as bits (electrons) leaked between thin-walled cells.

optane 3d xpoint

"The big deal is you're not building these [3D NAND] skyscrapers one floor at a time. We know how to go from 24 layers to 36 layers to 48 layers to 64 layers and so on," Sivaram said in an interview with Computerworld earlier this year. "There are no physics limitations to this. What we now have in 3D NAND is a predictable scaling for three and four generations -- something we never had before."

Sivaram said he is already planning for 3D NAND chips with more than 100 layers.

"We don't see a natural limit to how high we can go. If I went around and asked how high can we go, [NAND manufacturers] won't tell me we can take it to 96 or 126 layers, and there's a physical limit there," Sivaram said. "This has been our dream for a long time."

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Earlier this year, Intel and Micron began shipping 3D NAND flash drives with up to 3.5TB of capacity in an M.2 expansion card.

Copyright © 2016 IDG Communications, Inc.

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