Israeli start-up Anobit Technologies Ltd. emerged from quiet mode today and announced its first product, a multilevel cell (MLC) solid-state drive that it says is as reliable as today's higher-end and higher-cost single-level cell (SLC) enterprise-class flash drives.
Anobit said its Genesis SSDs extend standard MLC endurance from about 3,000 to more than 50,000 write/erase cycles, an improvement of 20 times over the average consumer-class drive today -- making MLC technology suitable for high-duty cycle applications such as relational databases.
The drives come in 200GB or 400GB capacities with Serial ATA interfaces. Through the use of an external bridge, they are capable of using the serial-attached SCSI (SAS) or Fibre Channel protocol. The drives have a sustained sequential read rate of 220MB/sec. and a sustained sequential write rate of 180MB/sec., according to Anobit.
Anobit, which was founded in 2006 and has raised more than $40 million in venture capital, said it has created a special processor, called a Memory Signal Processor, that boosts MLC NAND flash memory reliability through a special error-correction algorithm.
Gilad Engel, Anobit's vice president of business development, said the Memory Signal Processor adds an additional layer of error correction to the traditional error-correction code (ECC) that all SSD controllers have.
Engel said the 200GB Genesis SSD can handle 2TB worth of data writes per day for five years, and the 400GB SSD can sustain 4TB of writes per day. Both drives can achieve a write rate of 20,000 I/Os per second and a read rate of 30,000 IOPS, according to Engel.
The drives have native support for 512-, 520- and 528-byte block sizes and have a nonvolatile cache memory that's immune to power failures.
Engel would not offer any pricing for the drives, only saying that they would be "very competitive" with today's enterprise-class SLC SSDs.
According to Gregory Wong, an analyst at research firm Forward Insights, Anobit is not alone among SSD processor makers in producing technologies to extend MLC NAND's reliability. For example, Sandforce makes a processor that uses data compression and RAID architecture to get around the limitations of MLC.
Sandforce uses "24-bit/512-byte ECC hard coding. However, the fundamental issue is that the signal quality is declining, and Anobit's technology helps to get a 'cleaner' signal," Wong said.
The overhead for hardware-based signal decoding is relatively high, with some NAND flash vendors allocating up to 7.5% of the flash chip as spare area for ECC. Increasing the ECC hardware decoding capability not only increases the overhead further, but the effectiveness also declines with NAND's decreasing signal-to-noise ratio, Wong said.
Manufacturers over time have been able to shrink the geometric size of the circuitry that makes up NAND flash technology from 90 nanometers a few years ago to 25nm to 34nm today. The process of laying out the circuitry is known as lithography. Most manufacturers are using lithography processes in the 30nm-to-40nm range. Micron, Intel and Samsung are using 34nm, and Toshiba is using 32nm. Intel recently announced it has begun using a 25nm process.
The smaller the lithography process is, the more data can be fit on a single NAND flash chip. At 25nm, the cells in silicon are 3,000 times thinner than a strand of human hair. But as geometry shrinks, so too does the thickness of the walls that make up the cells that store bits of data. As the walls become thinner, more electrical interference, or "noise," can pass between them, becoming a tougher obstacle to tackle as it creates more data errors. The amount of noise compared to the data that can be read by a NAND flash controller is known as the signal-to-noise ratio.