3D chips: The next electronics revolution

New chip-design technology promises higher performance and lower power consumption

To accomplish anything in the suburbs, you need to get in your car and drive to another address. Downtown, in a skyscraper, you just use an elevator.

Elevators are more efficient -- and the semiconductor industry has taken notice (metaphorically speaking) with a trend toward 3D chip design. Instead of putting dies in separate packages, soldered to a circuit board and sending data through their I/O ports to other chips (i.e., driving through the suburbs), dies are stacked and data is moved from one layer to the next (i.e., via the elevator).

Chip industry insiders, such as Brian Cronquist, vice president at Monolithic 3D Inc., a 3D chip technology startup in San Jose, say that a 3D design using two stacked dies with 22-nanometer geometry would produce much the same result -- including reduced wire length, gate size and device power consumption -- as moving to one die with 15nm geometry. (According to Intel, a 22nm transistor's gates are so small that over 4,000 of them could fit across the width of a single human hair.)

3D processors

Further, this move could happen without spending about $5 billion to retool a fab for smaller geometry. Total capital and R&D costs for retooling for 3D would be closer to $200 million, Cronquist estimates, citing figures from Milpitas, Calif.-based GlobalFoundries, the former manufacturing arm of chip maker AMD.

Scaling up -- that is, stacking silicon -- "now looks as good as scaling down" -- or moving to smaller geometries, says Cronquist. "Previously, we were solving problems in 2D by adding more transistors and more metal layers, but that gets very expensive over time."

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