Micron ships Hybrid Memory Cube that boosts DRAM 15X

System makers get their first look at the high-speed memory boards

Micron Wednesday said that it's started shipping engineering samples of its 3D Hybrid Memory Cube (HMC) to high-performance computing and network equipment makers.

The technology changes the basic structure of DRAM by stacking layers of volatile memory dies one atop the other. Each of the layers are connected via new Vertical Interconnect Access (VIA) input/output (I/O) technology to a processor that sits at the base of the stack. Each memory layer has up to 2GB of capacity.

VIA is a method of passing an electrical wire vertically through a silicon wafer.

Text about this image
A photo of a stacked hybrid memory module

The first HMC boards will deliver 2GB and 4GB of capacity, providing aggregate bi-directional bandwidth of up to 160GBps compared to DDR3's 11GBps of aggregate bandwidth and DDR4, with 20GBps to 24GBps of aggregate bandwidth.

"For quite some time memory and logic was tracking well, following Moore's Law. But, as the processor market took a lead in performance, we started falling behind in trying to keep up with improvements generation over generation," said Mike Black, chief technology strategist for Micron's Hybrid Memory Cube team. "Processors with multiple core were being starved for memory."

HMC bandwidth varies depending on how many links a manufacturer chooses to use in a system; up to four links to the memory stick's processor can be enabled at a time allowing multiple lanes of serial connectivity.

Each link to the processor can run at different throughput speeds depending on how a manufacturer configures the memory chip: 10Gbps 12.5Gbps or 15Gbps line rate speeds are available.

The new HMC chips use up to 70% less energy per bit than existing DRAM technologies, which dramatically lowers the total cost of ownership, according to Black.

The HMC specification is backed by 100 tech companies The three largest memory makers, Micron, Samsung and Hynix, announced the final specifications for three-dimensional DRAM, which is aimed at increasing performance for networking and high performance computing markets.

While it is initially targeted toward high-end apps, the Memory Cube is expected to migrate down to mobile apps in the next three to five years as energy efficiency in the chip is further refined.

An illustration of a Hybrid Memory Cube connecting over a bus to a CPU

Lucas Mearian covers storage, disaster recovery and business continuity, financial services infrastructure and health care IT for Computerworld. Follow Lucas on Twitter at @lucasmearian, or subscribe to Lucas's RSS feed . His email address is lmearian@computerworld.com.

Copyright © 2013 IDG Communications, Inc.

7 inconvenient truths about the hybrid work trend
Shop Tech Products at Amazon