Back from the grave, it's Thursday's IT Blogwatch: in which IBM's embedded DRAM is smaller, faster, cooler. Not to mention a new multitouch demo from Jeff Han's Perceptive Pixel...
Ben Ames reports from San Francisco:
IBM plans to double the performance of its microprocessors in 2008 by using smaller, more efficient memory, according to a paper presented at the ISSCC (International Solid State Circuits Conference) trade show in San Francisco Wednesday. IBM plans to use dynamic RAM (DRAM) instead of static RAM (SRAM) as the embedded memory cache built onto each chip. The change will allow each chip to store its data in one-third the area and use one-fifth the electricity for standby power.
...
The approach will vastly improve chip performance for multicore processors and for applications that need to move large amounts of graphic data, such as gaming, networking and image-intensive multimedia ... A typical commercial microprocessor like Intel Corp.'s Core 2 Duo devotes 60% of its surface area to memory ... Replacing that with eDRAM cells taking up just one-third as much space will allow chip designers to build smaller chips and reduce the "run lengths" -- the length of wire that data must travel as it commutes around the chip.
The announcement ... sets up a potential confrontation between I.B.M. and Intel over the design of microprocessors that will begin to be available commercially next year. While I.B.M. now appears to be planning to integrate ultrafast memory directly into its processors, Intel has been hinting that it will instead stack memory chips on top of its processors to achieve similar performance. Both companies are struggling with the challenge of quickly moving vast amounts of data inside processors that increasingly have multiple processing engines, or cores, to achieve faster performance.
...
The I.B.M. researchers said they had been able to reduce memory cycle times to less than 2 nanoseconds, roughly 10 times the performance of off-the-shelf dynamic random access memory, or DRAM, used in PCs.
Confused? Thomas Ricker burbles this summary:
Embedded DRAM [is] at the bleeding edge of semiconductor news. Today, IBM's neo-maxi-zoom-dweebies will announce that their new type of memory will "triple" the amount of memory stored on computer chips while doubling the performance of processors. How you say? It's the SRAM, man. IBM's new eDRAM is faster than that scandalous DRAM -- nearly as fast as SRAM while taking up less space. As a result, IBM can replace most of the SRAM with the new, smaller eDRAM.
Still confused? Jeremy Steele has a go:
SRAM is typically used for CPU caches. It is really fast, but very expensive and isn’t very big either. DRAM comes in much larger sizes, costs a lot less, but has typically been viewed as being “too slow”. IBM has changed that, and the result is a new type of embedded DRAM memory called eDRAM. eDRAM will help speed up the performance of multi-core chips, and it is also good for graphics.
So, has IBM found the holy grail of memory? Who knows, and who cares. All I want is a fast computer that doesn’t cost $2,000.
Eric Bangeman decodes it for us:
While DRAM is familiar to anyone who has upgraded the memory on his or her PC, it's not suitable for use with CPUs due to its relatively high latencies. The much-faster SRAM has proven its utility for on-die cache, but uses a lot of die space. IBM's POWER6 CPU, the subject of a Monday presentation at ISSCC, will sport 8MB of L2 SRAM cache, which will take up a lot of room.
IBM says that it has a 65nm prototype eDRAM running with 1.5ns latency and 2ns random cycle time—speeds that are competitive with current SRAM ... Big Blue's plans for eDRAM will come into focus with the transition to a 45nm process in 2008. Both the Cell CPU used in the PlayStation 3 and the POWER CPUs will eventually utilize eDRAM for L2 cache. Given AMD's partnership with IBM, eDRAM could also find its way into the CPUs of Intel's rival.
RAM speed is one of the biggest bottlenecks on your system. It's called a cache miss. When your CPU tries to access data outside its local cache, it has to wait for that cache line to come from system RAM. Your CPU currently spends a huge fraction of its execution time doing that. If IBM can provide a significantly faster type of system RAM, they can reduce that huge fraction, which would noticeably speed up the entire system.
Cache misses are also the whole reason why hyperthreading ended up being a good idea: it minimizes the amount of time wasted during cache misses. If system RAM was always able to deliver memory without any latency, there would not have been any point to hyperthreading.
For reference, a cache miss typically costs something around 1-200 cycles ... While SRAM uses six transistors per bit, DRAM uses one transistor and one capacitor. This could give something around three times the density, allowing CPU manufacturers to triple the amount of cache without increasing die size. Bigger cache means fewer cache misses, which means less time spent doing nothing.
The sweet spot will probably be for L3 caches, that are already slow by cache standards, but a whole lot faster than system memory. Since L3 caches are large, the cost savings for switching to eDRAM would be largest there. As for power concerns, DRAM is higher than SRAM, but a larger L3 cache may reduce the traffic through the memory controller, and out to the DIMMs, which will probably more than make up for any increase in power density in the cache.
Deja vu? stevesliva clarifies why this is news:
IBM is announcing that the performance is on par with SRAM, and because they have integrated their deep-trench eDRAM process with the SOI process used for their Power CPUs. The result? 3x the cache on the die. IBM has offered embedded DRAM with bulk technologies for a few generations, but this is the first real SOI annoucement.
Buffer overflow:
Around the Net
Around Computerworld Previously in IT Blogwatch
- Good Morning Silicon Valley: Video thrilled the radio star
- Peter Lattman: Microsoft Settles Iowa Antitrust Class-Action :-(
- Security Incite: 2007 Security Incites
- 1 Raindrop: Question of Risk
- StorageMojo: Pumps, Pipes & Pools
- Geertjan: Hello OpenOffice.org API
- Valleywag: YAHOO MUSIC: Dave Goldberg, Bob Roback out at Yahoo
- Ryan Paul: SCO tries to subpoena Groklaw blogger
- Mike, Techdirt: Latest Threat To Clog The Internet: Bird Flu
And finally... More Multitouch from Jeff Han
Richi Jennings is an independent technology and marketing consultant, specializing in email, blogging, Linux, and computer security. A 20 year, cross-functional IT veteran, he is also an analyst at Ferris Research. Contact Richi at blogwatch@richi.co.uk.