Samsung achieves DDR3 size, calls it an efficiency breakthrough
Consumers should see significant savings on mobile battery life
Computerworld - Samsung this week announced a breakthrough in the evolution of smaller, more efficient DRAM memory. The company has produced its first 20nm, 4Gbit DDR3 DRAM.
As with all semiconductor technology, the smaller the transistors, the more capacity can go into a form factor. The smaller the circuitry, the cheaper it is to manufacture chips with the same or even greater capacity.
The DDR3 is used in desktops, notebooks, ultrabooks and tablets where Samsung said "customers will see a significant power savings," as well as cost savings.
"While we cannot speak for [device manufacturers], we believe that customers will benefit from a significantly lower total cost of ownership," a Samsung spokesman said in an email reply to Computerworld.
Samsung is already providing the new DDR3 chips to some manufacturers, and it expects that they will be available in computing devices later this year.
Over the past five years, Samsung has shrunk its DRAM transistors from 50nm (in 2009) to 30nm (in 2010) to 25nm (in 2011) to the 20nm process technology today.
While NAND flash has the lead in the race toward single-digit nanometer processes (it has been at 19nm for some time), DRAM circuitry is decisively more difficult to shrink.
With DRAM memory, each cell consists of a capacitor (where the electrical charge is held) and a transistor that are linked to one another, whereas with NAND flash memory each cell only has a transistor. So DRAM technology requires both the transistor and capacitor to shrink.
Samsung said it was able to refine its DRAM design and manufacturing technologies and came up with a "modified double patterning and atomic layer deposition."
In micro-circuitry, such as DRAM or NAND flash, dense repeating nanostructures are required. Atomic layer deposition (ALD) is a technique for depositing those nanostructures using thin films with precise uniformity. Double patterning, simply put, is a method for doubling the number of features.
Samsung's said its modified double patterning technology is a milestone. By enabling 20nm DDR3 production using current photolithography equipment, it has established a new core technology for the next generation of 10nm-class DRAM production.
Samsung also successfully created ultrathin dielectric layers of cell capacitors with an unprecedented uniformity, which has resulted in higher cell performance.
Applying new process innovations, Samsung's new 4Gbit 20nm DDR3 has improved manufacturing productivity by more than 30% over that of the preceding 25 nanometer DDR3, and more than twice that of 30nm-class DDR3, the company said.
"Also our new 20nm 4Gb DDR3-based modules can save up to 25% of the energy consumed by equivalent modules fabricated using the previous 25 nanometer process technology," Samsung said.
This article, Samsung achieves DDR3 size, calls it efficiency breakthrough, was originally published at Computerworld.com.
Lucas Mearian covers consumer data storage, consumerization of IT, mobile device management, renewable energy, telematics/car tech and entertainment tech for Computerworld. Follow Lucas on Twitter at @lucasmearian or subscribe to Lucas's RSS feed . His e-mail address is email@example.com.
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