First look: Dell Opteron server cranks up the cores with AMD 'Interlagos'

InfoWorld - It's an odd juxtaposition. The Dell PowerEdge R715 sits in a rack just below a recently decommissioned 2U, two-socket server that cost about as much when it was new five years ago. The difference? The older server has a total of two CPU cores, one per processor. The R715 has 32 cores, running at the same clock speed. If that's not progress, I don't know what is.

The R715 has been around since February (see InfoWorld's review), so strictly speaking, it's not a new server version. What's new: the R715's twin 16-core AMD Opteron "Interlagos" CPUs and support for 1,600MHz DDR3 RAM. Best of all, existing R715 systems can be upgraded to support the new chips with nothing more than a BIOS update. Otherwise, Interlagos is a drop-in replacement for Magny-Cours.

[ Also on InfoWorld: Stress test: AMD Opteron Magny-Cours versus Intel Xeon Nehalem-EX | Virtualization shoot-out: Citrix, Microsoft, Red Hat, and VMware ]

Like Magny-Cours before it, Interlagos promises to bring unbeatable price-performance to heavily multithreaded workloads such as virtualization. It costs considerably less than its closest Intel counterparts and offers twice the cores of the leading Intel chip. However, Interlagos is based on a new core architecture that is not yet supported by a number of popular operating systems (more on that below).

AMD Opteron 6200: Big guns, new design The AMD Opteron 6200-series Interlagos CPUs have 16 cores and 16 threads, each of which has a dedicated core. However, as the first Opteron based on AMD's new modular architecture, the Interlagos chip is built from eight Bulldozer modules. Each module, in turn, has two independent processors, but the FPU, fetch, decode, and execute units are shared. It's not quite the same as having 16 completely independent cores.

That said, Interlagos also supports Advanced Vector Extensions (AVX), which essentially double the width of the FPU, from 128 to 256 bits. The AVX extensions should produce greater floating-point performance, but only if the code explicitly supports them. Whether these changes result in a performance boost or a bottleneck will be highly dependent on the workload, as heavily threaded processes lacking AVX support that hit the FPU frequently may see some slowdown.

Clearly, the Bulldozer architecture is significantly different than AMD's previous major CPU iterations, and AMD appears to be positioning new architectures for the future to reduce the dependency on the FPU. AMD's Fusion system, which essentially moves FPU duties to a GPU, would be one example. It may be that whatever bottlenecks are present now will be mitigated later once various libraries and applications have been updated to take advantage of these new hardware designs. One definite bonus with Interlagos (and Bulldozer in general) is the addition of the AES-NI instructions that dramatically reduce computation times for AES encryption.