Computerworld -
To accomplish anything in the suburbs, you need to get in your car and drive to another address. Downtown, in a skyscraper, you just use an elevator.
Elevators are more efficient -- and the semiconductor industry has taken notice (metaphorically speaking) with a trend toward 3D chip design. Instead of putting dies in separate packages, soldered to a circuit board and sending data through their I/O ports to other chips (i.e., driving through the suburbs), dies are stacked and data is moved from one layer to the next (i.e., via the elevator).
Chip industry insiders, such as Brian Cronquist, vice president at Monolithic 3D Inc., a 3D chip technology startup in San Jose, say that a 3D design using two stacked dies with 22-nanometer geometry would produce much the same result -- including reduced wire length, gate size and device power consumption -- as moving to one die with 15nm geometry. (According to Intel, a 22nm transistor's gates are so small that over 4,000 of them could fit across the width of a single human hair.)
To continue reading, register here to become an Insider. You'll get free access to premium content from CIO, Computerworld, CSO, InfoWorld, and Network World. See more Insider content
or sign in.
Computerworld - To accomplish anything in the suburbs, you need to get in your car and drive to another address. Downtown, in a skyscraper, you just use an elevator.
Elevators are more efficient -- and the semiconductor industry has taken notice (metaphorically speaking) with a trend toward 3D chip design. Instead of putting dies in separate packages, soldered to a circuit board and sending data through their I/O ports to other chips (i.e., driving through the suburbs), dies are stacked and data is moved from one layer to the next (i.e., via the elevator).
Chip industry insiders, such as Brian Cronquist, vice president at Monolithic 3D Inc., a 3D chip technology startup in San Jose, say that a 3D design using two stacked dies with 22-nanometer geometry would produce much the same result -- including reduced wire length, gate size and device power consumption -- as moving to one die with 15nm geometry. (According to Intel, a 22nm transistor's gates are so small that over 4,000 of them could fit across the width of a single human hair.)
Further, this move could happen without spending about $5 billion to retool a fab for smaller geometry. Total capital and R&D costs for retooling for 3D would be closer to $200 million, Cronquist estimates, citing figures from Milpitas, Calif.-based GlobalFoundries, the former manufacturing arm of chip maker AMD.
Scaling up -- that is, stacking silicon -- "now looks as good as scaling down" -- or moving to smaller geometries, says Cronquist. "Previously, we were solving problems in 2D by adding more transistors and more metal layers, but that gets very expensive over time."
[Read about other chip-level advances that could change the industry.]
Rob Willoner, a technology analyst at Intel, acknowledges that the idea goes back several decades. But in the past, 3D design usually involved wire bonding, where one package is placed atop another and their peripheral wires are then connected.
Another method is to remove those wires completely and have the interconnects go straight through the top chip rather than around the periphery, though its silicon substrate to the chip below, using though-silicon vias (TSV.) "That is what they call 3D," says Willoner.
Going up
TSVs are essentially tiny shafts filled with copper that let electrical connections pass from the bottom of the wafer straight upward to the circuits on the top. Herbert Reiter, president of Eda2asic Consulting in Los Altos, Calif., notes that the computer industry wants TSVs to be no wider than 5 microns, so there will be room for plenty of TSVs on the chips and so they won't dwarf the nanometer-scale transistors to the point of causing connection problems.
With standard production methods, the shafts have an aspect ratio of 10-to-1. So with 5-micron TSVs, the silicon wafers would need to be 50 microns thick.
Similar TSVs are already used in large-scale production of image sensors, but those are typically 20 microns to 50 microns in diameter, Reiter adds. He says he has seen TSVs that are 2 microns wide and he has heard reports of 1-micron TSVs being developed in labs.
With today's technology, "we can make wafers" that are 50 microns thick, he notes. "Handling them is a challenge, but the advantages are compelling."
With the dies being connected directly to each other with TSVs, the interconnects between devices are now microns long rather than millimeters long, cutting signal latency by orders of magnitude, since a micron is a thousandth of a millimeter, Reiter notes. Also, buffer and repeater circuits for off-chip I/O are no longer needed -- that's a boon because such circuits often account for 20% to 40% of a chip's power consumption.
Developing 3D chips that consume 50% less power than 2D chips is a goal that's "definitely achievable," Reiter says.
Beyond that, with 3D chip technology, "you could combine analog, DRAM and logic devices and bring them together at the last moment, and mix and match different layers and change the functionality of the end product at a late stage in the design cycle at a fairly low cost," says Sitaram Arkalgud, director of the interconnect division of Sematech, a semiconductor industry consortium based in Albany, N.Y.
Layering memory atop a processor is widely cited as a potential use of the technology. It could speed up access to memory and reduce the real estate consumed by the circuits.
A height limit of 700 microns is common in the mobile market, and with the plastic packaging and solder connection bumps, that would leave room for a logic layer and four memory layers, says Sesh Ramaswami, senior director of strategy at Applied Materials, a Sunnyvale, Calif.-based provider of equipment and services to the semiconductor manufacturing industry.
On the desktop, multicore processors face significant delays when they access off-chip RAM. "But with memory stacked on the CPU, the RAM is only 50 microns away," notes Reiter. The memory could also just as easily be manufactured with an older technology with a larger, less expensive geometry, to reduce production costs, he adds.
With all its potential advantages, "just in the last six to 12 months I have seen enormous momentum, since 3D promises to be much more cost-effective for medium- and low-volume production than going to smaller feature sizes," Reiter observes.
Free Insider Guide