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Samsung now producing DDR 2.0 NAND flash, touts 3X performance gain

New flash is made using 20-nanometer circuitry

May 13, 2011 02:37 PM ET

Computerworld - Samsung Electronics announced that it is now producing high-performance DDR 2.0 multi-level-cell (MLC) memory chips based on its smallest 20-nanometer (nm) circuitry. The chips boast a performance improvement of three times over the company's current chip technology and have 64 gigabits of capacity, twice what Samsung had been producing with DDR 1.0 technology.

The chip will be used in mobile devices such as smartphones, tablets and solid-state drives (SSDs), Samsung said.

Equipped with a toggle DDR (Double Data Rate) 2.0 interface, the new 64Gbit chip can transmit data at a bandwidth of up to 400MB/sec.

DDR NAND flash comes in two forms: Toggle Mode from Samsung and Toshiba; and ONFI NAND, from the Open NAND Flash Interface (ONFI) working group.

The ONFI protocol is used by flash manufacturers such as Intel, Micron, SanDisk. Hynix and Spansion. In March, the ONFI working group announced its 3.0 specification for the DDR 2 interface with up to 400MB/sec throughput.

DDR 2.0 provides a 10-fold increase over 40MB/sec Single Data Rate (SDR) NAND flash in widespread use today. The new flash memory also triples the performance over 133MB/sec toggle DDR 1.0, 32Gbit NAND flash memory, which Samsung and Toshiba have been producing since 2009. "With this 20nm-class, 64Gbit, toggle DDR 2.0 NAND, Samsung is leading the market, which is evolving to fourth-generation smartphones and SATA 6Gbit/sec SSDs," Wanhoon Hong, executive vice president of memory sales & marketing for Samsung Electronics, said in a statement.

Samsung said its high-bandwidth toggle DDR 2.0 is expected to better support the ongoing shift toward advanced interfaces, as more mobile and consumer electronics devices requiring added performance and higher densities adopt new interfaces such as USB 3.0 and SATA 6.0Gbit/sec.

Further, the new 64Gbit MLC NAND chip offers an approximate 50% increase in productivity over 20nm-class 32Gbit MLC NAND chips with a toggle DDR 1.0 interface (which Samsung started producing in April 2010) and more than doubles the productivity of 30nm-class 32Gbit MLC NAND.

Lucas Mearian covers storage, disaster recovery and business continuity, financial services infrastructure and health care IT for Computerworld. Follow Lucas on Twitter at Twitter @lucasmearian or subscribe to Lucas's RSS feed Mearian RSS. His e-mail address is lmearian@computerworld.com.

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