MIT researchers develop method to draw finer linewidths on chips

IDG News Service - Researchers at MIT say they have made a breakthrough with light technology that eventually could help chip makers create integrated circuits with finer line widths than are now possible.

The researchers have developed a way to focus beams of light for chip manufacturing uses on a scale far smaller than was previously possible, said Rajesh Menon, a research engineer at MIT's department of electrical engineering and computer science.

Chip makers depend on light beams to draw circuit patterns on semiconductors, but most of the techniques currently being used can't produce patterns that are narrower than the wavelength of light itself.

The MIT researchers said their new approach enables extremely narrow lines to be drawn by combining beams of light at different wavelengths. The technique uses so-called interference patterns, in which different wavelengths of light sometimes reinforce each other while canceling each other out in other locations on a chip.

The technique is still as much as five years away from commercial use, the researchers said. But they claimed that once it's perfected, it could enable chip makers to build interconnects and transistors with lines as narrow as a single molecule, or just two to three nanometers wide.

That should have both performance and cost benefits, according to Menon. "If you make your transistors smaller, they typically work faster, [and] you get more functionality," he said, adding that manufacturing costs should go down as well.

Chip manufacturers such as Intel Corp. and Advanced Micro Devices Inc. typically imprint semiconductor designs on a glass material called a photomask, which is then used to transfer the pattern onto silicon wafers.

"What Intel does is pattern replication," Menon said, noting that the current approaches used by Intel and other companies involve the use of electron beams. MIT's new technique involves direct pattern creation via light sources, which can be more accurate and provides increased flexibility for quickly changing designs, the researchers claim.

"If you do patterning with electron beams, you will always have to worry about accuracy," Menon said. "Your patterns could get slightly distorted, which could have a big impact on device performance. Photons will go where you tell them to go, whereas electrons won't at the nanoscale."

At this point, the researchers have managed to produce circuitry lines that are 36 nanometers wide, which actually is wider than the 32nm line widths that Intel is starting to use in chips.

However, the line widths supported by the new technique are expected to become much narrower over time. Eventually, the researchers plan to commercialize the methodology through an MIT spin-off called LumArray Inc., according to Menon. "It's a ways out, as we have to solve some material and technical issues," he said.

Menon acknowledged that the technique could hit a wall when it does get down to the atomic scale. "The question then becomes, Can you make the molecule smaller?" he said. "You're probably limited then."

A paper about the research that led to the development of the new technique was due to be published in last Friday's issue of Science magazine.

This is the second time in less than a year that MIT researchers have announced a methodology for shrinking the size of semiconductors. Last July, a separate group detailed an approach for using nanotechnology to produce chips with 25nm line widths.