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3D chips: The next electronics revolution


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New chip-design technology promises higher performance and lower power consumption

To accomplish anything in the suburbs, you need to get in your car and drive to another address. Downtown, in a skyscraper, you just use an elevator.

Elevators are more efficient -- and the semiconductor industry has taken notice (metaphorically speaking) with a trend toward 3D chip design. Instead of putting dies in separate packages, soldered to a circuit board and sending data through their I/O ports to other chips (i.e., driving through the suburbs), dies are stacked and data is moved from one layer to the next (i.e., via the elevator).

Chip industry insiders, such as Brian Cronquist, vice president at Monolithic 3D Inc., a 3D chip technology startup in San Jose, say that a 3D design using two stacked dies with 22-nanometer geometry would produce much the same result -- including reduced wire length, gate size and device power consumption -- as moving to one die with 15nm geometry. (According to Intel, a 22nm transistor's gates are so small that over 4,000 of them could fit across the width of a single human hair.)

Looking good for 2013

Looking ahead, Sematech's Arkalgud predicts that the first generation of volume-production 3D devices will come out in 2013. That, he says, "will start two races, in scaling and in stacking, as people use them in more products." Scaling refers to adding more, smaller TSVs, while stacking means adding more layers.

"In four or five years, those races will shake out. And looking beyond, we will be adding more devices to stacks, such as optical interconnects, sensors and micro-electromechanical systems," he adds. "This is not evolutionary, this is revolutionary, definitely."

Using 2.5D allows "much larger devices than we could normally build on one piece of silicon," Madden says. "To produce the largest devices, we use four separate die that are interconnected using an interposer." It is easier to get acceptable production yields with four independent die rather than one large die, he says.

"The second application is where we can integrate different generations on the same interposer, so we can optimize the technology," Madden says. Xilinx "will not be stacking Intel CPUs" on top of each other, he explains, adding "that problem is not solvable" because of the hundreds of connector pins required. But Xilinx will put DRAM on top of processors, he adds.

"2.5D has a lot of advantages," agrees Rich Wawrzyniak, an analyst at Semico Research in Phoenix. One is that manufacturers don't have to fabricate the interposer at the same technology level as the other ICs in the system. Vendors could make the active silicon at 20nm and make the interposer at 65nm, save costs and have a better yield.

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